ALU Instructions
Key Concepts |
|
Terms
| Term | Meaning |
|---|---|
| ALU | The arithmetic and logic unit (ALU) is a component in the CPU that preforms mathematic and logical functions. |
| Base Register | A general-purpose register whose value is used as the starting address when computing a memory address with an offset; used by LDR and STR (encoded in IR[8:6]). |
| Branching | A technique that causes a program to change the flow of its execution; e.g., if/else and calling a function. |
| Clock Cycle | A single time segment, controlled by the computer's clock, in which circuits receive input values, process the inputs, and then produce an output. |
| Condition Code (CC) | Information about the previous instruction's result. Can indicate that the previous instruction resulted in an error/exception, overflow/underflow, or positive/zero/negative value |
| Control Unit | The part of the CPU that sequences micro-operations during instruction execution; directs the ALU, registers, and memory interface but does not perform memory reads or writes itself. |
| DR (Destination Register) | The general-purpose register designated to receive a value loaded from memory or computed by an instruction (encoded in IR[11:9]). |
| Effective Address | The final memory address computed by an instruction, for example by adding Off9 to the PC; the address stored in DR by the LEA instruction. |
| FDE Cycle | The Fetch-Decode-Execute pattern used by the CPU to execute a single instruction. |
| Indirect Address | A memory address stored at another memory location; used by LDI and STI to reach data anywhere in the full 16-bit address space, beyond the PCOffset9 range. |
| Instruction | Single executable line of code in a program. Contains OpCode and Operands. |
| IR (Instruction Register) | A CPU register that holds the instruction currently being executed; loaded from memory during the Fetch phase and decoded to identify the opcode and operands. |
| ISA | Instruction Set Architecture. LIst of all Instruction OpCode and expected Operands. |
| MAR (Memory Address Register) | A CPU register that holds the address of the memory location to be read from or written to; set by the Control Unit before each memory cycle. |
| MDR (Memory Data Register) | A CPU register that holds the data value being transferred to or from memory; written by a memory read and read by the Control Unit after a memory cycle completes. |
| Memory | Storage used by the program to save and retrieve data. This storage is external to the CPU. |
| Memory Cycle | A single read or write operation between the CPU and memory; may require one or more cycles to complete depending on memory speed. |
| Memory Unit | The hardware component responsible for reading data from and writing data to memory; operates outside the Control Unit and communicates through MAR and MDR. |
| Off6 | A 6-bit signed offset sign-extended to 16 bits, added to a Base Register to compute a memory address; used by LDR and STR. |
| Off9 (PCOffset9) | A 9-bit signed offset sign-extended to 16 bits, added to the PC to compute a memory address; used by LD, ST, LDI, STI, and LEA. |
| OpCode | Assembly instruction keyword as defined by the ISA. |
| Operand(s) | Assembly instruction parameters, as defined by the ISA. |
| PC (Program Counter) | A CPU register that holds the address of the next instruction to be fetched; automatically incremented by 1 after each Fetch phase. |
| Register | Storage used by the CPU to save and retrieve data. These devices directly connected to the CPU's control device and the ALU. |
| Sign Extension (SExt) | The process of expanding a shorter bit-width value (e.g., 6-bit or 9-bit) to 16 bits by copying the sign bit into all upper bit positions, preserving the value's sign. |
| SR (Source Register) | The general-purpose register that supplies the value to be written to memory in a store instruction (encoded in IR[11:9]). |
| Subroutines | Subset of branching that has added capabilities like passing parameters, throwing exceptions, and returning results. |
| TRAP Routines | Functions that are built-in to the programming language; e.g., System.out.println() in Java. |
Introductions
The LC-3 ALU is capable of executing three (3) operations: ADD, AND, and NOT. Although limited, when combined, these three (3) operations can be used to do many more things that add and compare.
In this section we will review the ALU instructions, options for each, and look at some simple example code.
ADD
ADD: LC-3 ISA Format
| OpCode | DR | SR1 | Mode | IMM5 |
|---|---|---|---|---|
| 0001 | 000 | 000 | 1 | 00000 |
Examples
ADD R3, R1, #1 ; Add values in register 1 with 1, store result in R3
ADD R3, R2, #-4 ; Add values in register 2 with -4, store result in R3
ADD R3, R3, xB ; Add value in R3 to hex value B, store result in R3
ADD R3, R3, b0111 ; Add value in R3 to binary value 7, store result in R3
| OpCode | DR | SR1 | Mode | unused | SR2 |
|---|---|---|---|---|---|
| 0001 | 000 | 000 | 0 | 00 | 000 |
Examples
ADD R3, R1, R2 ; sum values in registers 1 and 2, store result in R3
ADD R3, R2, R2 ; Add R2 to itself, store result in R3
ADD R3, R3, R3 ; Add value in R3 to itself, store result in R3
ADD: Explanation
ADD is the only arithmetic operation in the LC-3 ISA. This command adds 2 16-bit, 2's complement values. The result is stored in a register
The Condition Code (CC) register is updated based on the resulting addition
ADD has 2 modes:
- Register Mode: Add values from 2 register
- Immediate Mode: Add value in 1 register with a hard coded immediate value
- Immediate value is represented in 5-bits
- Immediate value is a 2's complement
- -16 to +15
ADD: Examples
General Syntax
ADD DR, SR1, SR2- DR - Destination Register for resulting operation
- SR1 and SR2 - Source registers for the operation
ADD DR, SR1, Imm5- DR - Destination Register for resulting operation
- SR1 - Source register for the operation
- Imm5 - 5-bit 2's complement value to add to SR1
Add registers and store in a different register
ADD R0, R1, R2Add the values in R1 and R2. Store in R0
ADD R0, R1, #6Add the value in R1 and 6. Store in R0
Add registers and store in a one of the same registers
ADD R1, R1, R2Add the values in R1 and R2. Store in R1, overwriting the original value in R1
ADD R1, R1, #-3Add the value in R1 and -3. Store in R1, overwriting the original value in R1
Add a register to itself and store in a different register
ADD R0, R1, R1Add the values in R1 to itself (double the original value). Store in R0
Add a register to itself and store in the same registers
ADD R1, R1, R1Add the values in R1 to itself (double the original value). Store in R1, overwriting the original value in R1
ADD: Gotchas
- Immediate Value mode can only add a register value and a small number (-16 to +15). To add larger values, use Register mode
- ADD and AND are easy to mix up when typing source code. Double check when you type these instructions. If your program behaves unexpectedly around and ADD instruction, check that you didn't accidentally type AND
AND
AND: LC-3 ISA Format
| OpCode | DR | SR1 | Mode | IMM5 |
|---|---|---|---|---|
| 0101 | 000 | 000 | 1 | 00000 |
Examples
AND R3, R1, #1 ; And values in register 1 with 1, store result in R3
AND R3, R2, #-4 ; And values in register 2 with -4, store result in R3
AND R3, R3, xB ; And value in R3 to hex value B, store result in R3
AND R3, R3, b0111 ; Add value in R3 to binary value 7, store result in R3
| OpCode | DR | SR1 | Mode | unused | SR2 |
|---|---|---|---|---|---|
| 0101 | 000 | 000 | 0 | 00 | 000 |
Examples
AND R3, R1, R2 ; And values in registers 1 and 2, store result in R3
AND R3, R2, R2 ; And R2 to itself, store result in R3
AND R3, R3, R3 ; And value in R3 to itself, store result in R3
AND: Explanation
AND is one of two logic operations in the LC-3 ISA. This command bitwise ands 2 16-bit values. The result is stored in a register
The Condition Code (CC) register is updated based on the resulting and operation.
AND has 2 modes:
- Register Mode: And values from 2 register
- Immediate Mode: And value in 1 register with a hard coded immediate value
- Immediate value is represented in 5-bits
- -16 to +15
- Immediate value is represented in 5-bits
AND: Examples
AND DR, SR1, SR2- DR - Destination Register for resulting operation
- SR1 and SR2 - Source registers for the operation
AND DR, SR1, Imm5- DR - Destination Register for resulting operation
- SR1 - Source register for the operation
- Imm5 - 5-bit 2's complement value to AND to SR1
AND registers and store in a different register
AND R0, R1, R2And the values in R1 and R2. Store in R0
AND R0, R1, #6And the value in R1 and 6. Store in R0
AND registers and store in a one of the same registers
AND R1, R1, R2And the values in R1 and R2. Store in R1, overwriting the original value in R1
AND R1, R1, #-3And the value in R1 and -3. Store in R1, overwriting the original value in R1
AND a register to itself and store in a different register
AND R0, R1, R1And the values in R1 to itself (double the original value). Store in R0
AND a register to itself and store in the same registers
AND R1, R1, R1And the values in R1 to itself (double the original value). Store in R1, overwriting the original value in R1
AND: Gotchas
- Immediate Value mode can only add a register value and a small number (-16 to +15). To add larger values, use Register mode
- The Immediate Value will be sign-extended, Remember that the most significant bits [15-5] will be all zeros (0) or ones (1) based on the sign
- ADD and AND are easy to mix up when typing source code. Double check when you type these instructions. If your program behaves unexpectedly around and AND instruction, check that you didn't accidentally type ADD
NOT
NOT: LC-3 ISA Format
| OpCode | DR | SR | unused |
|---|---|---|---|
| 1001 | 000 | 000 | 000000 |
Examples
NOT R3, R3 ; Not value in R3, store result in R3
NOT R3, R2 ; Not value in R2, store result in R3
NOT: Explanation
NOT is the other logic operations in the LC-3 ISA. This command bitwise nots a 16-bit value. The result is stored in a register
The Condition Code (CC) register is updated based on the resulting negation.
NOT: Examples
NOT DR, SR- DR - Destination Register for resulting operation
- SR - Source register for the operation
NOT register and store in a different register
NOT R0, R1Not the value in R1. Store in R0
NOT register and store in the same register
NOT R1, R1Not the value in R1. Store in R0, overwriting the original value in R1
NOT: Gotchas
The LC-3 Simulate tool shows Hex and Decimal values of 16-bit data stored in Memory and Registers. Simulate does this 'to be helpful' to the developer. When storing data for logical operations, it falls to the developer to remember that the bits are representing bits.
Conclusion
The LC-3 Arithmetic Logic Unit (ALU) is capable of performing one (1) arithmetic instruction, ADD, and two (2) logic functions (AND, NOT).
ADD and AND have two (2) modes that define the input data elements to use. Register mode pulls data from two (2) registers. Immediate mode pulls data from one (1) register and a hard-coded value that is defined in the instruction.
Once the CPU Controller has all the information to complete an ALU instruction, it send the data and operation to the ALU to complete. Results are send back to the Controller to store.