Instruction Anatomy

Key Concepts

Each instruction in LC-3 uses 16 bits Because the LC-3 is a 16-bit architecture, each instruction is 16 bits. These bits for each instruction are divided into parts that the CPU Controller can reference to orchestrate the CPU to complete each instruction Each instruction takes multiple clock cycles to complete Depending on the complexity of each instruction, it will take varying clock cycles to complete an instruction The CPU Controller follows a Fetch-Decode-Execute routine to execute instructions The CPU Controller follows a fixed set of steps to complete each instruction: Fetching the instruction, decoding its 16 bits, and executing it. Some instructions require additional steps for memory access.

Terms

Term	Meaning
ALU	The arithmetic and logic unit (ALU) is a component in the CPU that preforms mathematic and logical functions.
Base Register	A general-purpose register whose value is used as the starting address when computing a memory address with an offset; used by LDR and STR (encoded in IR[8:6]).
Branching	A technique that causes a program to change the flow of its execution; e.g., if/else and calling a function.
Clock Cycle	A single time segment, controlled by the computer's clock, in which circuits receive input values, process the inputs, and then produce an output.
Condition Code (CC)	Information about the previous instruction's result. Can indicate that the previous instruction resulted in an error/exception, overflow/underflow, or positive/zero/negative value
Control Unit	The part of the CPU that sequences micro-operations during instruction execution; directs the ALU, registers, and memory interface but does not perform memory reads or writes itself.
DR (Destination Register)	The general-purpose register designated to receive a value loaded from memory or computed by an instruction (encoded in IR[11:9]).
Effective Address	The final memory address computed by an instruction, for example by adding Off9 to the PC; the address stored in DR by the LEA instruction.
FDE Cycle	The Fetch-Decode-Execute pattern used by the CPU to execute a single instruction.
Indirect Address	A memory address stored at another memory location; used by LDI and STI to reach data anywhere in the full 16-bit address space, beyond the PCOffset9 range.
Instruction	Single executable line of code in a program. Contains OpCode and Operands.
IR (Instruction Register)	A CPU register that holds the instruction currently being executed; loaded from memory during the Fetch phase and decoded to identify the opcode and operands.
ISA	Instruction Set Architecture. LIst of all Instruction OpCode and expected Operands.
MAR (Memory Address Register)	A CPU register that holds the address of the memory location to be read from or written to; set by the Control Unit before each memory cycle.
MDR (Memory Data Register)	A CPU register that holds the data value being transferred to or from memory; written by a memory read and read by the Control Unit after a memory cycle completes.
Memory	Storage used by the program to save and retrieve data. This storage is external to the CPU.
Memory Cycle	A single read or write operation between the CPU and memory; may require one or more cycles to complete depending on memory speed.
Memory Unit	The hardware component responsible for reading data from and writing data to memory; operates outside the Control Unit and communicates through MAR and MDR.
Off6	A 6-bit signed offset sign-extended to 16 bits, added to a Base Register to compute a memory address; used by LDR and STR.
Off9 (PCOffset9)	A 9-bit signed offset sign-extended to 16 bits, added to the PC to compute a memory address; used by LD, ST, LDI, STI, and LEA.
OpCode	Assembly instruction keyword as defined by the ISA.
Operand(s)	Assembly instruction parameters, as defined by the ISA.
PC (Program Counter)	A CPU register that holds the address of the next instruction to be fetched; automatically incremented by 1 after each Fetch phase.
Register	Storage used by the CPU to save and retrieve data. These devices directly connected to the CPU's control device and the ALU.
Sign Extension (SExt)	The process of expanding a shorter bit-width value (e.g., 6-bit or 9-bit) to 16 bits by copying the sign bit into all upper bit positions, preserving the value's sign.
SR (Source Register)	The general-purpose register that supplies the value to be written to memory in a store instruction (encoded in IR[11:9]).
Subroutines	Subset of branching that has added capabilities like passing parameters, throwing exceptions, and returning results.
TRAP Routines	Functions that are built-in to the programming language; e.g., System.out.println() in Java.

Introduction to LC-3 Instruction Anatomy

All commands are 16-bits in length. The bits are partitioned into OpCodes and Operands. During execution of an LC-3 command, the Simulate's control unit examines the instruction (which was loaded into the IR at the start of execution)

The control unit parses the 16-bits of the IR and causes the system to perform a series of steps to complete execution of that command.

The number of clock cycles required to complete a command will vary with the steps needed to complete it

Opcodes and Operands

LC-3 ISA — 16-bit instruction encoding

Instruction	Opcode [15:12]				Operands [11:0]
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADD (reg)	0001				DR			SR1			0	00		SR2
ADD (imm)	0001				DR			SR1			1	imm5
AND (reg)	0101				DR			SR1			0	00		SR2
AND (imm)	0101				DR			SR1			1	imm5
BR	0000				n	z	p	PCoffset9
JMP	1100				000			BaseR			000000
JSR	0100				1	PCoffset11
JSRR	0100				0	00		BaseR			000000
LD	0010				DR			PCoffset9
LDI	1010				DR			PCoffset9
LDR	0110				DR			BaseR			offset6
LEA	1110				DR			PCoffset9
NOT	1001				DR			SR			111111
RTI	1000				000000000000
ST	0011				SR			PCoffset9
STI	1011				SR			PCoffset9
STR	0111				SR			BaseR			offset6
TRAP	1111				0000				trapvect8
Reserved	1101				—

Bits [15,12] of each 16-bit command are the OpCode. This 4-bit string is unique for each command.

Bits [11,0] are the Operands (parameters) for each Opcode/Command. Depending on the command, some bits of the Operands are not used, and left as zero (0).

The LC-3 ISA defines the commands, and each bit in the command string that the Simulate environment will reference to execute each command.

Opcode

During the execution of a command, Simulate loads the new command into the IR. It will use the IR to determine the OpCode and, later in the command execution, Operands needed to complete the command.

Why are Operands determined later in the command execution?

Reviewing the commands, above, notice that some commands use the 12-bit Operand portion of the command different than others.

Some are the same, but others are different.

The Control Unit (from von Neumann's Model) that orchestrates the execution of each command cannot parse the Operands until it knows the Opcode. From the OpCode, the Control Unit can correctly parse the remaining 12 bits of the IR into the correct parameters to execute the command as the programmer intended.

Operands

The remaining 12 bits are parsed based on the OpCode. The control unit extracts the important bits into information used to complete the command

Dest Reg

Commands that store results in a register use 3 bits to identify the register

Src Reg / Src Reg 1 / Src Reg 2

Commands that read data from a register use 3 bits to identify the register. Commands that use two (2) source registers are noted with 1 and 2.

Imm Val

Immediate values are hard-coded numbers that are assembled directly into the command. The LC-3 has a special mode for immediate values in the ADD and AND commands.

Base Reg

A 3-bit address of a general register that contains a base value for some Load/Store commands

PC Offset

A 6- or 9-bit value that is added to the PC register for Load/Store and Branch instructions.

Trap Vector

An 8-bit value of a built-in TRAP function. This value is the memory address of a lookup table to the actual TRAP function.

Referencing Registers

Recall that the LC-3 has eight (8) general registers that user programs and Simulate share. In assembly source code, the registers are identified by "R" and a number (i.e. R3, R7).

Src, Dest, and Base Registers included in Operands are all 3-bit values. The 3 bits address the register to be used in the Operands.

Source Code	Operand
R0	000
R1	001
R2	010
...	...
R7	111

Processing a Command

During the execution of a single command, the control unit will direct a series of events during several clock cycles. These events will cause the command to be loaded into the IR, operands to be moved to/from memory, register values to be loaded into the ALU, and the PC to be updated.

When performed in the correct order, these events will result in the command execution completing correctly.

There are six (6) possible events that can occur. Some commands do not require all six (6) events to occur.

All commands will require Fetch, Decode, and Execute events. Some commands will also require some or all of the other events.

This processing from the command unit is commonly called the Fetch-Decode-Execute cycle of an instruction.

If performed, the events are always performed in the following order:

Instruction Cycle Summary

Not all instructions follow all six phases. The minimum path is: Fetch → Decode → Execute

Instructions requiring memory access add: Fetch → Decode → Evaluate Address → Fetch Operands → Execute

Instructions storing results to memory or registers add: Fetch → Decode → Execute → Store Results

Instruction Type	Fetch	Decode	Eval Addr	Fetch Op	Execute	Store	Next PC
ALU (ADD, AND)	✓	✓			✓	✓	✓
Load (LD, LDR)	✓	✓	✓	✓	✓		✓
Store (ST, STR)	✓	✓	✓		✓	✓	✓
Branch (BR)	✓	✓	✓		✓		✓
TRAP	✓	✓	✓	✓	✓

Instruction Processing Flow

The following diagram illustrates the complete instruction processing cycle, showing how different instruction types follow different paths through the six phases:

Diagram Legend

Blue nodes — Required for every instruction (Fetch, Decode, Execute)
Orange nodes — Optional; used only by certain instruction types (Evaluate Address, Fetch Operands, Store Results)

Fetch

Diagram Legend

Blue nodes — Active fetch states (MAR ← PC, IR ← MDR, PC ← PC + 1)
Orange nodes — Memory-wait states (waiting for the memory interface to return data)

1. Transfer the current PC to the Memory Interface (MAR ← PC)
2. Wait for the Memory Interface to retrieve the data (MemoryFetch)
   • Memory Interface gets memory chunks until it has all 16 bits of the Instruction
3. Transfer the resulting data from the Memory Interface to IR (IR ← MDR)
4. Increment PC by 1 (PC ← PC + 1)

Recall that the PC contains the address of the next command to execute. At the start of Fetch, that address in PC is passed to the Memory Interface. After a few clock cycles, the Memory Interface will have the data (the next command) from that address.

The data is copied into the IR. The control unit has the command's 16 bits to parse and execute.

As part of the Fetch phase, the PC is incremented. At the end of Fetch contains the address of the next command to execute after the current command completes.

Example: If PC contains x3000, the control unit:

• Sends x3000 to memory
• Receives the instruction (e.g., 0001 001 010 0 00 011 for ADD R1, R2, R3)
• Loads it into IR
• Increments PC to x3001

Decode

The Decode phase examines the instruction bits in the IR to determine what operation to perform and prepare any necessary control signals.

Decode Process:

Diagram Legend

Blue nodes — Decode processing states (Extract Opcode, Parse Operands, Set Control Signals)
Green node — Branch enable calculation (Calculate BEN)

1. Extract Opcode - Read IR[15:12] to identify the instruction type
2. Parse Operands - Interpret IR[11:0] based on the opcode
   • Identify destination and source registers
   • Extract immediate values or offsets
   • Determine addressing modes
3. Set Control Signals - Prepare signals for subsequent phases
4. Calculate Branch Enable - Evaluate BEN ← IR[11] & N + IR[10] & Z + IR[9] & P
   • BEN (Branch Enable) is set if condition codes match the branch condition
   • IR[11] checks negative flag (N)
   • IR[10] checks zero flag (Z)
   • IR[9] checks positive flag (P)

Evaluate Addresses

Optional Event only used if the current command is a Load command or TRAP

1. Based on the specific Load instruction, calculate the address to load using Base Reg, PC Offset, and/or Trap Vector Operands
2. Retain the resulting address for the next event

If the Opcode will load data from Memory -or- is the TRAP instruction, the control unit must use sections of the Operands to calculate a 16-bit address from which to read data

• For PC Offset Operands, the address in the PC is added to the PC Offset
• For Base Reg Operands, the data in the general register identified in the Base Reg Operand is extracted
• For TRAP instruction, the Trap Vector Operand (sign extended to 16-bits) is extracted.

Fetch Operands

Optional Event only used if the current command is a Load command or TRAP

1. Load data from Memory
   1. Transfer the previously derived address to the Memory Interface
   2. Wait for the Memory Interface to retrieve the data
   3. Retain the resulting data for the next event

The control unit reads data from memory in preparation to execute the command.

For TRAP commands, the data returned from the Memory Interface is the address of the first instruction of the referenced TRAP instruction.

Execute

1. Complete the command execution, based on the Opcode
   • For ALU Commands
     1. Transfer data from Registers to the ALU
     2. Signal ALU to perform specific operation
     3. Retain result for Store Results phase
   • For Load Commands
     1. Transfer the previously loaded data into the specified Register
     2. Set CC based on value loaded
   • For Branch Commands
     1. Compare CC register to command's Operands
     2. If the same, copy the previously calculated address to the PC
   • For Jump Commands
     1. Copy PC to Register 7
     2. Copy previously calculated address to PC
   • For RET Command
     1. Copy R7 to PC
   • For TRAP commands
     1. Copy the previously calculated address to the PC

Store Results

Optional Event only used if the current command is an ALU or Store command

1. Write results to their destination, based on the Opcode
   • For ALU Commands
     1. Transfer ALU result to the specified Destination Register
     2. Set CC based on result
   • For Store Commands
     1. Transfer the destination address and data to the Memory Interface
     2. Wait for Memory Interface to complete write operation

Conclusion

Assembly instructions are made up of bit patterns that define the instruction (opcode) and parameters (operands). All LC-3 instructions are 16 bits in length, with the first 4 bits defining the opcode. The remaining bits can be used to identify data or modes used for that opcode.

Not all 16 bits are used in every instruction.

The controller in the CPU requires multiple cycles to execute a single instruction. The number of cycles depends on the instruction complexity. Simpler instructions take fewer cycles than complex ones.

All ISAs follow a Fetch-Decode-Execute cycle to complete each instruction. Some instructions include additional steps, typically to interface with memory for data management.